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Welcome to the Pipeline and Vector Processing MCQs Page

Dive deep into the fascinating world of Pipeline and Vector Processing with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Pipeline and Vector Processing, a crucial aspect of Computer Architecture. In this section, you will encounter a diverse range of MCQs that cover various aspects of Pipeline and Vector Processing, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Computer Architecture.

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Check out the MCQs below to embark on an enriching journey through Pipeline and Vector Processing. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Computer Architecture.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Pipeline and Vector Processing. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Pipeline and Vector Processing MCQs | Page 4 of 21

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Q31.
Which of the following architecture is/are not suitable for realizing SIMD ?

a.

Vector Processor

b.

Array Processor

c.

Von Neumann

d.

All of the above

Discuss
Answer: (c).Von Neumann
Q32.
CPU checks for an interrupt signal during

a.

Starting of last Machine cycle

b.

Last T-State of instruction cycle

c.

First T-State of interrupt cycle

d.

Fetch cycle

Discuss
Answer: (b).Last T-State of instruction cycle
Q33.
In a vectored interrupt

a.

the branch address is assigned to a fixed location in memory

b.

the interrupting source supplies the branch information to the processor through an interrupt vector

c.

the branch address is obtained from a register in the processor

d.

none of the above

Discuss
Answer: (b).the interrupting source supplies the branch information to the processor through an interrupt vector
Q34.
An instruction pipeline can be implemented by means of

a.

LIFO buffer

b.

FIFO buffer

c.

Stack

d.

None of the above

Discuss
Answer: (b).FIFO buffer
Q35.
A microprogram sequencer

a.

generates the address of next micro instruction to be executed.

b.

generates the control signals to execute a microinstruction.

c.

sequentially averages all microinstructions in the control memory.

d.

enables the efficient handling of a micro program subroutine.

Discuss
Answer: (a).generates the address of next micro instruction to be executed.
Q36.
Status bit is also called

a.

Binary bit

b.

Flag bit

c.

Signed bit

d.

Unsigned bit

Discuss
Answer: (b).Flag bit
Q37.
If the value V(x) of the target operand is contained in the address field itself, the addressing mode is

a.

immediate

b.

direct

c.

indirect

d.

implied

Discuss
Answer: (b).direct
Q38.
The instructions which copy information from one location to another either in the processor’s internal register set or in the external main memory are called

a.

Data transfer instructions

b.

Program control instructions

c.

Input-output instructions

d.

Logical instructions

Discuss
Answer: (a).Data transfer instructions
Q39.
Content of the program counter is added to the address part of the instruction in order to obtain the effective address is called

a.

relative address mode

b.

index addressing mode

c.

register mode

d.

implied mode

Discuss
Answer: (a).relative address mode
Q40.
Which of the following interrupt is non maskable

a.

INTR

b.

RST 7.5

c.

RST 6.5

d.

TRAP

Discuss
Answer: (d).TRAP
Page 4 of 21

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