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Welcome to the Memory Organization MCQs Page

Dive deep into the fascinating world of Memory Organization with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Memory Organization, a crucial aspect of Computer Architecture. In this section, you will encounter a diverse range of MCQs that cover various aspects of Memory Organization, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Computer Architecture.

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Check out the MCQs below to embark on an enriching journey through Memory Organization. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Computer Architecture.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Memory Organization. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Memory Organization MCQs | Page 8 of 23

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Q71.
The increase in the width of the cache address tag, can be done with the

a.

Process-identity tag

b.

Process-identifier term

c.

Process-identifier tag

d.

Process-identify tag

Discuss
Answer: (c).Process-identifier tag
Q72.
The victim buffer's performance and the operation is almost similar to

a.

Write buffer

b.

Read buffer

c.

Write-through

d.

Read through

Discuss
Answer: (a).Write buffer
Q73.
Assume that the hit-time is single clock cycle, independent of size of block, and then 16-byte block in a 4 KB cache will be having access-time of

a.

6.027 clock cycles

b.

8.077 clock cycles

c.

7.027 clock cycles

d.

8.027 clock cycles

Discuss
Answer: (d).8.027 clock cycles
Q74.
The virtual memory producing the virtual-addresses, are translated by

a.

Logical addresses

b.

Local addresses

c.

Physical addresses

d.

All above

Discuss
Answer: (c).Physical addresses
Q75.
The most obvious architectural parameter is the

a.

Physical pages

b.

Page sizes

c.

Page fault

d.

Block size

Discuss
Answer: (b).Page sizes
Q76.
The time of CPU can be modeled as

a.

(CPU execution clock cycles + Memory stall clock cycles) - Clock cycle time

b.

(CPU execution clock cycles x Memory stall clock cycles) + Clock cycle time

c.

(CPU execution clock cycles + Memory stall clock cycles)

d.

(CPU execution clock cycles / Memory stall clock cycles)

Discuss
Answer: (c).(CPU execution clock cycles + Memory stall clock cycles)
Q77.
The processor protection structure expand memory access protection from two levels to many, the added ones are

a.

Rings

b.

Frames

c.

Pages

d.

Blocks

Discuss
Answer: (a).Rings
Q78.
The virtually indexer's limitation, saying that a cache which is direct-mapped can have a size no bigger than the

a.

Page size

b.

Frame size

c.

Cache

d.

Block

Discuss
Answer: (a).Page size
Q79.
IA-32 allows the operating system to maintain the protection level of the called

a.

Rings

b.

Frames

c.

Pages

d.

Routine

Discuss
Answer: (d).Routine
Q80.
Per memory reference, the miss-rate can be turned into the per instruction misses rate by

a.

Miss rate= Memory accesses/ instructions

b.

Miss rate= Memory accesses* instructions

c.

Miss rate= Memory accesses-instructions

d.

Miss rate= Memory accesses+ instructions

Discuss
Answer: (a).Miss rate= Memory accesses/ instructions
Page 8 of 23

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