Q. The number of stages of the integer pipeline, U, of Pentium is

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Q. Which of the following is a cache of Pentium?

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Q. The speed of integer arithmetic of Pentium is increased to a large extent by

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Q. For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of

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Q. Which of the following is a class of architecture of MII (multiple instruction issue)?

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Q. The compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group in

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Q. The architecture in which the hardware decides which instructions are to be issued concurrently at run time is

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Q. The CPU has to wait until the execution stage to determine whether the condition is met in

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Q. The memory device that holds branch target addresses for previously executed branches is

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Q. The branch target buffer is

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Q. The stage in which the CPU fetches the instructions from the instruction cache in superscalar organization is

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Q. The CPU decodes the instructions and generates control words in

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Q. The fifth stage of pipeline is also known as

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Q. In the execution stage the function performed is

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Q. The stage in which the CPU generates an address for data memory references in this stage is

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Q. The feature of separated caches is

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Q. In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from

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Q. The FPU (Floating Point Unit) writes the results to the floating point register file in

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Q. The floating point multiplier segment performs floating point multiplication in

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Q. The instruction or segment that executes the floating point square root instructions is

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