Q. The CPU has to wait until the execution stage to determine whether the condition is met in

View solution

Q. The memory device that holds branch target addresses for previously executed branches is

View solution

Q. The branch target buffer is

View solution

Q. The stage in which the CPU fetches the instructions from the instruction cache in superscalar organization is

View solution

Q. The CPU decodes the instructions and generates control words in

View solution

Q. The fifth stage of pipeline is also known as

View solution

Q. In the execution stage the function performed is

View solution

Q. The stage in which the CPU generates an address for data memory references in this stage is

View solution

Q. The feature of separated caches is

View solution

Q. In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from

View solution

Q. The FPU (Floating Point Unit) writes the results to the floating point register file in

View solution

Q. The floating point multiplier segment performs floating point multiplication in

View solution

Q. The instruction or segment that executes the floating point square root instructions is

View solution

Q. The floating point rounder segment performs rounding off operation at

View solution

Q. Which of the following is a floating point exception that is generated in case of integer arithmetic?

View solution

Q. The mechanism that determines whether a floating point operation will be executed without creating any exception is

View solution

Q. Which of the following is not a transcendental instruction?

View solution

Q. The transcendental instruction that supports computation of sine and cosine is

View solution

Q. The instruction that computes tan(x) is

View solution

Q. The instruction that computes arctan(x) is

View solution