Q. The CPU decodes the instructions and generates control words in

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Q. The fifth stage of pipeline is also known as

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Q. In the execution stage the function performed is

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Q. The stage in which the CPU generates an address for data memory references in this stage is

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Q. The feature of separated caches is

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Q. In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from

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Q. The FPU (Floating Point Unit) writes the results to the floating point register file in

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Q. The floating point multiplier segment performs floating point multiplication in

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Q. The instruction or segment that executes the floating point square root instructions is

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Q. The floating point rounder segment performs rounding off operation at

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Q. Which of the following is a floating point exception that is generated in case of integer arithmetic?

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Q. The mechanism that determines whether a floating point operation will be executed without creating any exception is

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Q. Which of the following is not a transcendental instruction?

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Q. The transcendental instruction that supports computation of sine and cosine is

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Q. The instruction that computes tan(x) is

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Q. The instruction that computes arctan(x) is

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Q. The instruction, F2XMI, is used to compute

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Q. The instruction, FYL2XP, supports to compute the expression

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Q. The size of a general purpose floating point register of floating point unit is

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Q. For floating point operations, the bits used by mantissa in a floating point register is

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