Q. If CPL is greater than zero, then the instruction that remains unaffected is

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Q. The condition, “CPL not equals to zero” satisfies when executing the instruction

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Q. While executing the instruction IN/OUT, the condition of CPL is

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Q. The instruction at which the exception is generated, but the processor extension registers contain the address of failing instruction is

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Q. The exception that has no error code on a stack is

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Q. Which of the following is protected mode exception?

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Q. Which of the following operation is not carried out by 80286?

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Q. After completion of the first cycle, the first task is again scheduled for the next cycle. This process is known as

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Q. The operation that is provided by the internal architecture, to save the execution state of a task is

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Q. The instruction that can be used to carry out task switch operation is

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Q. The IRET instruction gets back the execution state of the previous task, if

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Q. The NT flag is set by the task switch operation, that is initiated by

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Q. The 80286 executes LMSW instruction to enter into

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Q. The instruction that sets the zero flag, if the segment referred to, by the selector can be read is

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Q. The instruction that sets the zero flag, if the segment referred to by the selector, can be written as

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Q. The instruction that reads the descriptor access rights byte into the register is

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Q. The instruction that reads the segment limit into the register, if privilege rules and descriptor type allow is

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Q. The instruction that adjusts the RPL (Requested Privilege Level) of the selector, to the numeric maximum of current selector RPL value is

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Q. Which of the following is a supporting chip of 80286?

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Q. In minimum mode, the function of 80286 is

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