Q. After completion of the first cycle, the first task is again scheduled for the next cycle. This process is known as

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Q. The operation that is provided by the internal architecture, to save the execution state of a task is

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Q. The instruction that can be used to carry out task switch operation is

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Q. The IRET instruction gets back the execution state of the previous task, if

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Q. The NT flag is set by the task switch operation, that is initiated by

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Q. The 80286 executes LMSW instruction to enter into

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Q. The instruction that sets the zero flag, if the segment referred to, by the selector can be read is

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Q. The instruction that sets the zero flag, if the segment referred to by the selector, can be written as

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Q. The instruction that reads the descriptor access rights byte into the register is

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Q. The instruction that reads the segment limit into the register, if privilege rules and descriptor type allow is

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Q. The instruction that adjusts the RPL (Requested Privilege Level) of the selector, to the numeric maximum of current selector RPL value is

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Q. Which of the following is a supporting chip of 80286?

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Q. In minimum mode, the function of 80286 is

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Q. The signal that is applied to the decoding logic, to differentiate between interrupt, code fetch and data bus cycles is

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Q. By adding which of the following, the minimum mode of 80286 gives the multibus interface of 80286?

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Q. The number of bus controllers that are used for interfacing of memory and I/O devices is

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Q. If the 80286 need to use system bus, then the signal that is to be active is

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Q. If MBYTES input is high, then the pin serves as

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Q. Latches are used in 80286 to

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Q. The I/O port addresses, that are not used, while designing practical systems around 80286 are

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