adplus-dvertising
frame-decoration

Question

A task with privilege level 0, doesn’t refer to all the lower level privilege descriptors in

a.

GDT (global descriptor table)

b.

LDT (local descriptor table)

c.

IDT (interrupt descriptor table)

d.

None of the mentioned

Answer: (b).LDT (local descriptor table)

Engage with the Community - Add Your Comment

Confused About the Answer? Ask for Details Here.

Know the Explanation? Add it Here.

Q. A task with privilege level 0, doesn’t refer to all the lower level privilege descriptors in

Similar Questions

Discover Related MCQs

Q. The selector RPL that uses a less trusted privilege than the current privilege level for further use is known as

Q. The effective privilege level is

Q. The task requesting an access to a descriptor is allowed to access after checking the

Q. A CALL instruction can reference only a code segment descriptor with

Q. The RPL of a selector that referred to the code descriptor must have

Q. The instruction that refers to only code segment descriptors with DPL equal to or less than the task CPL is

Q. When a JUMP instruction references a Task State Segment(TSS) descriptor, then DPL must be

Q. The data segment access refers to

Q. An exception is generated when

Q. The mechanism to provide protection, that is accomplished with the help of read/write privileges is

Q. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in

Q. The mechanism that is accomplished using descriptor usages limitations and rules of privilege check is

Q. The mechanism that is executed at certain privilege levels, determined by CPL (Current Privilege Level) and I/O privilege level (IOPL) is

Q. If CPL is not of the required privilege level, then the instructions that get affected is

Q. If CPL is greater than zero, then the instruction that remains unaffected is

Q. The condition, “CPL not equals to zero” satisfies when executing the instruction

Q. While executing the instruction IN/OUT, the condition of CPL is

Q. The instruction at which the exception is generated, but the processor extension registers contain the address of failing instruction is

Q. The exception that has no error code on a stack is

Q. Which of the following is protected mode exception?