Q. The processor without the structural hazard is

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Q. In the following instruction set DADD R1,R2,R3; DSUB R4,R1,R5; AND R6,R1,R7; OR R8,R1,R9; XOR R10,R1,R11, all the instructions after the DADD use the result of the

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Q. If any instruction in A1, . . . , A4, D, M1, . . . , M7 has the same register destination as this instruction, then the possible solution is

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Q. The simplest scheme to handle branches is to

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Q. Splitting the cache into separate instruction and data caches or by using a set of buffers, usually called

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Q. The ideal CPI (Cycle per instruction) on a pipelined processor is almost always

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Q. With the separate adder and a branch decision made during ID, there is only a

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Q. A stall is commonly called a

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Q. The load instruction has a delay or latency that cannot be eliminated by forwarding, other technique used is

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Q. If the event occurs at the same place every time the program is executed with the same data and memory allocation, then the event is known as

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Q. Pipeline overhead arises from the combination of pipeline register delay and

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Q. Each of the clock cycles from the previous section of execution, becomes a

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Q. When an instruction is stalled, all instructions issued later than the stalled instructio and hence not as far along in the pipeline, are also

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Q. The set of instructions examined as candidates for potential execution is called the

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Q. The effectiveness of any branch prediction scheme depends both on the accuracy of the scheme and the frequency of conditional branches, which vary in SPEC from

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Q. During the execution of DADD R1,R2,R3; DSUB R4,R1,R5; AND R6,R1,R7; OR R8,R1,R9; XOR R10,R1,R11, DSUB instruction reads the value during its ID stage. This problem is called a

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Q. Exceptions that occur within instructions are usually

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Q. When the compiler attempts to schedule instructions to avoid the hazard; this approach is called

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Q. Decoding is done in parallel with reading registers, which is possiblebecause the register specifiers are at a fixed location, the stated technique is called a

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Q. Pipelining increases the CPU instruction

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