Question
a.
1-clock-cycle stall on branches
b.
2-clock-cycles stall on branches
c.
3-clock-cycles stall on branches
d.
4-clock-cycles stall on branches
Posted under Computer Architecture
Engage with the Community - Add Your Comment
Confused About the Answer? Ask for Details Here.
Know the Explanation? Add it Here.
Q. With the separate adder and a branch decision made during ID, there is only a
Similar Questions
Discover Related MCQs
Q. A stall is commonly called a
View solution
Q. The load instruction has a delay or latency that cannot be eliminated by forwarding, other technique used is
View solution
Q. If the event occurs at the same place every time the program is executed with the same data and memory allocation, then the event is known as
View solution
Q. Pipeline overhead arises from the combination of pipeline register delay and
View solution
Q. Each of the clock cycles from the previous section of execution, becomes a
View solution
Q. When an instruction is stalled, all instructions issued later than the stalled instructio and hence not as far along in the pipeline, are also
View solution
Q. The set of instructions examined as candidates for potential execution is called the
View solution
Q. The effectiveness of any branch prediction scheme depends both on the accuracy of the scheme and the frequency of conditional branches, which vary in SPEC from
View solution
Q. During the execution of DADD R1,R2,R3; DSUB R4,R1,R5; AND R6,R1,R7; OR R8,R1,R9; XOR R10,R1,R11, DSUB instruction reads the value during its ID stage. This problem is called a
View solution
Q. Exceptions that occur within instructions are usually
View solution
Q. When the compiler attempts to schedule instructions to avoid the hazard; this approach is called
View solution
Q. Decoding is done in parallel with reading registers, which is possiblebecause the register specifiers are at a fixed location, the stated technique is called a
View solution
Q. Pipelining increases the CPU instruction
View solution
Q. Control hazards can cause a greater performance loss for MIPS pipeline than do
View solution
Q. The sum of the contents of the base register and the sign-extended offset is used as a memory address, the sum is known as
View solution
Q. The presence of antidependences and output dependences, leads to
View solution
Q. The process of letting an instruction move from the instruction decode stage into the execution stage of this pipeline is usually called
View solution
Q. To solve the problems with a simple hardware technique called forwarding, also known as
View solution
Q. Every MIPS instruction can be implemented in at most
View solution
Q. Code containing redundant loads, stores, and other operations that might be eliminated by an optimizer, is a
View solution
Suggested Topics
Are you eager to expand your knowledge beyond Computer Architecture? We've curated a selection of related categories that you might find intriguing.
Click on the categories below to discover a wealth of MCQs and enrich your understanding of Computer Science. Happy exploring!