Q. If (address line) Ao=0 then, the status of address and memory are

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Q. If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be

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Q. The advantage of dynamic RAM is

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Q. Whenever a large memory is required in a microcomputer system, the memory subsystem is generally designed using

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Q. If a typical static RAM cell requires 6 transistors then corresponding dynamic RAM requires

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Q. To store the charge as a representation of data, the basic dynamic RAM cell uses

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Q. The process of refreshing the data in the RAM to reduce the possibility of data loss is known as

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Q. The field in which dynamic RAM is more complicated than static RAM is

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Q. Memory refresh activity is

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Q. The number of memory chips that are enabled at a time for refresh activity is

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Q. A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold data charge level practically constant is

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Q. If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’ denotes the range of time it may take then, refresh time (tr) can be defined as

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Q. The device that enables the microprocessor to read data from the external devices is

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Q. The example of output device is

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Q. The input and output operations are respectively similar to the operations,

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Q. The operation, IOWR (active low) performs

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Q. The latch or IC 74LS373 acts as

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Q. While performing read operation, one must take care that much current should not be

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Q. To avoid loading during read operation, the device used is

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Q. The chip 74LS245 is

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