Q. The operation, IOWR (active low) performs

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Q. The latch or IC 74LS373 acts as

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Q. While performing read operation, one must take care that much current should not be

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Q. To avoid loading during read operation, the device used is

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Q. The chip 74LS245 is

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Q. In 74LS245, if DIR is 1, then the direction is from

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Q. In memory-mapped scheme, the devices are viewed as

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Q. Programmable peripheral input-output port is another name for

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Q. Port C of 8255 can function independently as

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Q. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called

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Q. The data bus buffer is controlled by

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Q. The input provided by the microprocessor to the read/write control logic is

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Q. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor is

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Q. The port that is used for the generation of handshake lines in mode 1 or mode 2 is

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Q. If A1=0, A0=1 then the input read cycle is performed from

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Q. The function, ‘data bus tristated’ is performed when

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Q. The pin that clears the control word register of 8255 when enabled is

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Q. In the I/O mode, the 8255 ports work as

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Q. In BSR mode, only port C can be used to

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Q. The feature of mode 0 is

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