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Welcome to the Microcontroller 8051 MCQs Page

Dive deep into the fascinating world of Microcontroller 8051 with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Microcontroller 8051, a crucial aspect of Microprocessor. In this section, you will encounter a diverse range of MCQs that cover various aspects of Microcontroller 8051, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Microprocessor.

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Check out the MCQs below to embark on an enriching journey through Microcontroller 8051. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Microprocessor.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Microcontroller 8051. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Microcontroller 8051 MCQs | Page 2 of 13

Q11.
The first byte of a short jump instruction represents
Discuss
Answer: (a).opcode byte
Q12.
Which of the following is not an addressing mode of 8051?
Discuss
Answer: (d).none of the above
Q13.
The symbol, ‘addr 16’ represents the 16-bit address which is used by the instructions to specify the
Discuss
Answer: (c).destination address of call or jump
Q14.
The external interrupts of 8051 can be enabled by
Discuss
Answer: (d).all of the mentioned
Q15.
The bits that control the external interrupts are
Discuss
Answer: (c).EX0 and EX1
Discuss
Answer: (c).enable or disable all the interrupts
Q17.
The number of priority levels that each interrupt of 8051 have is

a.

1

b.

2

c.

3

d.

4

Discuss
Answer: (b).2
Q18.
The priority level of interrupt of 8051 for which SI(serial interrupt) interrupt is programmed is
Discuss
Answer: (b).level 1
Q19.
The interrupt bit that when set works at level 1, and otherwise at level 0 is
Discuss
Answer: (d).all of the mentioned
Q20.
All the interrupts at level 1 are polled in the second clock cycle of the
Discuss
Answer: (b).fifth T state
Page 2 of 13

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