Q. The number of priority levels that each interrupt of 8051 have is

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Q. The priority level of interrupt of 8051 for which SI(serial interrupt) interrupt is programmed is

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Q. The interrupt bit that when set works at level 1, and otherwise at level 0 is

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Q. All the interrupts at level 1 are polled in the second clock cycle of the

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Q. The 8259-A is a _________.

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Q. ______ is used to transfer data between microprocessor and I/O process.

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Q. The registers that contain the status information is

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Q. Which of the following register can be addressed as a byte?

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Q. Which of the following is bit-addressable register?

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Q. The higher and lower bytes of a 16-bit register DPTR are represented respectively as

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Q. The register that is used for accessing external data memory is

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Q. Among the four groups of register banks, the number of groups that can be accessed at a time is

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Q. The number of 8-bit registers that a register bank contain is

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Q. If RS1=1, RS0=0, then the register bank selected is

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Q. If RS1=1, RS0=1, then the register bank selected is

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Q. The PCON register consists of

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Q. The on-chip oscillator is stopped in

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Q. In idle mode, the device that is disabled is

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Q. The only way to terminate the power down mode is to

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Q. The idle mode can be terminated by

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