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Welcome to the 8051 Microcontroller MCQs Page

Dive deep into the fascinating world of 8051 Microcontroller with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of 8051 Microcontroller, a crucial aspect of Computer Architecture. In this section, you will encounter a diverse range of MCQs that cover various aspects of 8051 Microcontroller, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Computer Architecture.

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Check out the MCQs below to embark on an enriching journey through 8051 Microcontroller. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Computer Architecture.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of 8051 Microcontroller. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

8051 Microcontroller MCQs | Page 7 of 14

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Q61.
When any interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?

a.

to the next instruction which is to be executed

b.

to the first instruction of ISR

c.

to the first location of the memory called the interrupt vector table

d.

to the end of the program

Discuss
Answer: (c).to the first location of the memory called the interrupt vector table
Q62.
What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?

a.

0xFFH

b.

0x00H

c.

0x10H

d.

0xF0H

Discuss
Answer: (b).0x00H
Q63.
After RETI instruction is executed then the pointer will move to which location in the program?

a.

next interrupt of the interrupt vector table

b.

next instruction of the program after the IE instruction

c.

next instruction after the RETI in the memory

d.

none of the mentioned

Discuss
Answer: (b).next instruction of the program after the IE instruction
Q64.
Which pin of the external hardware is said to exhibit INT0 interrupt?

a.

pin no 10

b.

pin no 11

c.

pin no 12

d.

pin no 13

Discuss
Answer: (c).pin no 12
Q65.
Which bit of the IE register is used to enable TxD/RxD interrupt?

a.

IE.D5

b.

IE.D2

c.

IE.D3

d.

IE.D4

Discuss
Answer: (d).IE.D4
Q66.
Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assuming initially all bits of the IE register are zero)?

a.

EX0=1

b.

EA=1

c.

any of the mentioned

d.

both of the mentioned

Discuss
Answer: (d).both of the mentioned
Q67.
Why normally LJMP instructions are the topmost lines of the ISR?

a.

so as to jump to some other location where there is a wider space of memory available to write the codes

b.

so as to avoid overwriting of other interrupt instructions

c.

both of the mentioned

d.

none of the mentioned

Discuss
Answer: (c).both of the mentioned
Q68.
Which register is used to make the pulse a level or a edge triggered pulse?

a.

TCON

b.

IE

c.

IPR

d.

SCON

Discuss
Answer: (a).TCON
Q69.
What is the disadvantage of a level triggered pulse?

a.

a constant pulse is to be maintained for a greater span of time

b.

difficult to analyse its effects

c.

it is difficult to produce

d.

another interrupt may be caused, if the signal is still low before the completion of the last instruction

Discuss
Answer: (d).another interrupt may be caused, if the signal is still low before the completion of the last instruction
Q70.
What is the correct order of priority that is set after a controller gets reset?

a.

TxD/RxD > T1 > T0 >EX1 > EX0

b.

TxD/RxD < T1 < T0<EX1 < EX0

c.

EX0 > T0 > EX1 >T1> TxD/RxD

d.

EX0 < T0 < EX1 < T1 < TxD/RxD

Discuss
Answer: (c).EX0 > T0 > EX1 >T1> TxD/RxD
Page 7 of 14

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