Q. A processor needs software interrupt to

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Q. A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged

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Q. Which is the most appropriate match for the items in the first column with the items in the second column:

X. Indirect Addressing I. Array implementation
Y. Indexed Addressing II. Writing re-locatable code
Z. Base Register Addressing III. Passing array as parameter

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Q. The 2’s complement representation of (−539)10 in hexadecimal is

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Q. A device employing INTR line for device interrupt puts the CALL instruction on the data bus while

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Q. In 8085, which of the following modifies the program counter ?

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Q. The 2' s complement representation of the decimal value - 15 is

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Q. Sign extension is a step in

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Q. In 2' s complement addition, overflow

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Q. In the absolute addressing mode

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Q. What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program?

MVI L, 5DH
MVI L, 6BH
MOV A, H
ADD L

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Q. The performance of a pipelined processor suffers if

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Q. Horizontal microprogramming :

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Q. Assuming all numbers are in 2's complement representation, which of the following numbers is divisible by 11111011?

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Q. For a pipelined CPU with a single ALU, consider the following situations

1. The j + 1-st instruction uses the result of the j-th instruction
as an operand
2. The execution of a conditional jump instruction
3. The j-th and j + 1-st instructions require the ALU at the same
time

Which of the above can cause a hazard ?

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Q. Consider the grammar rule E → E1 - E2 for arith­metic expressions. The code generated is targeted to a CPU having a single user register. The sub­traction operation requires the first operand to be in the register. If E1 and E2 do not have any com­mon sub expression, in order to get the shortest possible code

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Q. If 73x (in base-x number system) is equal to 54y (in base-y number system), the possible values of x and y are

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Q. Which of the following addressing modes are suitable for program relocation at run time ?

(i) Absolute addressing
(ii) Based addressing
(iii) Relative addressing
(iv) Indirect addressing

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Q. Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is

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Q. A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be

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