Q. Which interfacing method lowers the speed of the processor?

View solution

Q. What is EDO RAM?

View solution

Q. What is RDRAM?

View solution

Q. Which of the following can transfer up to 1.6 billion bytes per second?

View solution

Q. Which of the following cycle is larger than the access time?

View solution

Q. Which mode of operation selects an internal page of memory in the DRAM interfacing?

View solution

Q. What is the maximum time that the RAS signal can be asserted in the page mode operation?

View solution

Q. Which of the following mode of operation in the DRAM interfacing has a page boundary?

View solution

Q. Which mode offers the banking of memory in the DRAM interfacing technique?

View solution

Q. Which of the following has a fast page mode RAM?

View solution

Q. Which mode reduces the need for fast static RAMs?

View solution

Q. Which of the following is also known as hyper page mode enabled DRAM?

View solution

Q. What does BEDO DRAM stand for?

View solution

Q. Which of the following is more quickly accessed?

View solution

Q. Which factor determines the effectiveness of cache?

View solution

Q. Which of the following determines a high hit rate of the cache memory?

View solution

Q. Which of the following is a common cache?

View solution

Q. Which factor determines the number of cache entries?

View solution

Q. What is the size of the cache for an 8086 processor?

View solution

Q. How many possibilities of mapping does a direct mapped cache have?

View solution