Q. Which of the following can transfer up to 1.6 billion bytes per second?

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Q. Which of the following cycle is larger than the access time?

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Q. Which mode of operation selects an internal page of memory in the DRAM interfacing?

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Q. What is the maximum time that the RAS signal can be asserted in the page mode operation?

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Q. Which of the following mode of operation in the DRAM interfacing has a page boundary?

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Q. Which mode offers the banking of memory in the DRAM interfacing technique?

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Q. Which of the following has a fast page mode RAM?

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Q. Which mode reduces the need for fast static RAMs?

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Q. Which of the following is also known as hyper page mode enabled DRAM?

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Q. What does BEDO DRAM stand for?

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Q. Which of the following is more quickly accessed?

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Q. Which factor determines the effectiveness of cache?

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Q. Which of the following determines a high hit rate of the cache memory?

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Q. Which of the following is a common cache?

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Q. Which factor determines the number of cache entries?

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Q. What is the size of the cache for an 8086 processor?

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Q. How many possibilities of mapping does a direct mapped cache have?

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Q. Which of the following allows speculative execution?

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Q. Which of the following refers to the number of consecutive bytes which are associated with each cache entry?

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Q. Which factor determines the cache performance?

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