Q. How many possibilities of mapping does a direct mapped cache have?

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Q. Which of the following allows speculative execution?

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Q. Which of the following refers to the number of consecutive bytes which are associated with each cache entry?

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Q. Which factor determines the cache performance?

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Q. What are the basic elements required for cache operation?

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Q. How many divisions are possible in the cache memory based on the tag or index address?

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Q. Which of the following cache has a separate comparator for each entry?

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Q. What type of cache is used in the Intel 80486DX?

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Q. Which of the following has a separate cache for the data and instructions?

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Q. Which type of cache is used the SPARC architecture?

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Q. Which of the following approach uses more silicon area?

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Q. Which of the following cache mapping can prevent bus thrashing?

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Q. Which cache mapping have a sequential execution?

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Q. Which address is used for a tag?

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Q. In which of the following the data is preserved within the cache?

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Q. What is the disadvantage of the physical address?

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Q. Which cache memory solve the cache coherency problem?

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Q. Which of the following is the biggest challenge in the cache memory design?

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Q. What arises when a copy of data is held both in the cache and in the main memory?

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Q. In which writing scheme does all the data writes go through to main memory and update the system and cache?

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