Q. What is the main disadvantage in the software refresh of the DRAM?

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Q. Which refresh technique is useful for low power consumption?

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Q. Which refreshing techniques generates a recycled address?

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Q. Which of the following uses a software refresh in the DRAM ?

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Q. How do CBR works?

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Q. Which of the refresh circuit is similar to CBR?

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Q. Which technology is standardized in DRAM for determining the maximum time interval between the refresh cycle?

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Q. In which pin does the data appear in the basic DRAM interfacing?

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Q. What is the duration for memory refresh to remain compatible?

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Q. Which interfacing method lowers the speed of the processor?

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Q. What is EDO RAM?

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Q. What is RDRAM?

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Q. Which of the following can transfer up to 1.6 billion bytes per second?

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Q. Which of the following cycle is larger than the access time?

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Q. Which mode of operation selects an internal page of memory in the DRAM interfacing?

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Q. What is the maximum time that the RAS signal can be asserted in the page mode operation?

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Q. Which of the following mode of operation in the DRAM interfacing has a page boundary?

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Q. Which mode offers the banking of memory in the DRAM interfacing technique?

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Q. Which of the following has a fast page mode RAM?

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Q. Which mode reduces the need for fast static RAMs?

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