Question
a.
Get the data
b.
Get the address of the module
c.
Get the address of the data within the module
d.
None of the above
Posted under Computer Architecture
Engage with the Community - Add Your Comment
Confused About the Answer? Ask for Details Here.
Know the Explanation? Add it Here.
Q. In memory interleaving, the lower order bits of the address is used to
Similar Questions
Discover Related MCQs
Q. Which of the following technique/s used to effectively utilize main memory ?
View solution
Q. The transfer of large chunks of data with the involvement of the processor is done by _______ .
View solution
Q. The BOOT sector files of the system are stored in _____ .
View solution
Q. The DMA differs from the interrupt mode by
View solution
Q. The DMA transfers are performed by a control circuit called as
View solution
Q. In DMA transfers, the required signals and addresses are given by the
View solution
Q. After the complition of the DMA transfer the processor is notified by
View solution
Q. The DMA controller has _______ registers.
View solution
Q. The DMA controller is connected to the ____
View solution
Q. The technique where the controller is given complete access to main memory is
View solution
Q. The controller uses _____ to help with the transfers when handling network interfaces.
View solution
Q. To overcome the conflict over the possession of the BUS we use ______.
View solution
Q. The registers of the controller are ______.
View solution
Q. When process requests for a DMA transfer ,
View solution
Q. The DMA transfer is initiated by _____
View solution
Q. Consider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________.
View solution
Q. A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.
View solution
Q. How many address bits are required to represent a 32 K memory
View solution
Q. How many address bits are required to represent 4K memory
View solution
Q. Which of the following memories stores the most number of bits?
View solution
Suggested Topics
Are you eager to expand your knowledge beyond Computer Architecture? We've curated a selection of related categories that you might find intriguing.
Click on the categories below to discover a wealth of MCQs and enrich your understanding of Computer Science. Happy exploring!
