Q. The DMA transfers are performed by a control circuit called as

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Q. In DMA transfers, the required signals and addresses are given by the

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Q. After the complition of the DMA transfer the processor is notified by

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Q. The DMA controller has _______ registers.

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Q. The DMA controller is connected to the ____

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Q. The technique where the controller is given complete access to main memory is

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Q. The controller uses _____ to help with the transfers when handling network interfaces.

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Q. To overcome the conflict over the possession of the BUS we use ______.

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Q. The registers of the controller are ______.

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Q. When process requests for a DMA transfer ,

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Q. The DMA transfer is initiated by _____

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Q. Consider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________.

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Q. A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.

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Q. How many address bits are required to represent a 32 K memory

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Q. How many address bits are required to represent 4K memory

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Q. Which of the following memories stores the most number of bits?

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Q. In a virtual memory system, the addresses used by the programmer belongs to

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Q. The method for updating the main memory as soon as a word is removed from the Cache is called

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Q. How many different addresses are required by the memory that contain 16K words?

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Q. What is the bit storage capacity of a ROM with a 512' 4-organization?

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