Q. Consider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________.

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Q. A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.

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Q. How many address bits are required to represent a 32 K memory

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Q. How many address bits are required to represent 4K memory

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Q. Which of the following memories stores the most number of bits?

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Q. In a virtual memory system, the addresses used by the programmer belongs to

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Q. The method for updating the main memory as soon as a word is removed from the Cache is called

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Q. How many different addresses are required by the memory that contain 16K words?

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Q. What is the bit storage capacity of a ROM with a 512' 4-organization?

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Q. How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes?

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Q. Which of the following technology can give high speed RAM?

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Q. In 8085 microprocessor how many I/O devices can be interfaced in I/O mapped I/O technique?

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Q. How many memory chips of (128 x 8) are needed to provide a memory capacity of 4096 x 16?

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Q. An attempt to access a location not owned by a Program is called

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Q. Cache memory works on the principle of

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Q. Memory interleaving technique is used to address the memory modules in order to have

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Q. In a multiprogramming system, which of the following is used

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Q. Associative memory is some times called as

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Q. A more efficient way to organise a Page Table is by means of an associative memory having

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Q. If there are four ROM ICs of 8K and two RAM ICs of 4K words, than the address range of Ist RAM is (Assume initial addresses correspond to ROMs)

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