Q. To solve the problems with a simple hardware technique called forwarding, also known as

View solution

Q. Every MIPS instruction can be implemented in at most

View solution

Q. Code containing redundant loads, stores, and other operations that might be eliminated by an optimizer, is a

View solution

Q. Delays arising from the use of a load result 1 or 2 cycles after the loads, refers as

View solution

Q. Situations that prevent the next instruction in the instruction stream, from executing during its designated clock cycle are known as

View solution

Q. The simplest dynamic branch-prediction scheme is a

View solution

Q. When an instruction is guaranteed to complete, it is called

View solution

Q. An implementation technique whereby multiple instructions are overlapped in execution, refers to

View solution

Q. Grouping the 16 functional units together into four groups and supplying a set of buses, called

View solution

Q. Example: the number of cars per hour and is determined by how often a completed car exits the assembly line, shows the

View solution

Q. To improve the ability of the compiler to fill branch delay slots, most processors with conditional branches have introduced a

View solution

Q. Pipelining that allows to achieve higher clock rates by decomposing the five-stage integer pipeline into eight stages, is refered as

View solution

Q. When all instructions take the same number of cycles, which must also equal the number of pipeline stages the process is known as

View solution

Q. Exceptions that are caused by some hardware event that is not under the control of the user program, refered as

View solution

Q. Hazards in pipelines can make it necessary to

View solution

Q. Indicating which of the four steps the instruction is in, is provided by

View solution

Q. In pipelines with long-running operations, the possible caused issue is called

View solution

Q. The effective pipeline speedup with branch penalties, assuming an ideal CPI of 1, is

View solution

Q. For execution, branch instructions require 2 cycles, store instructions require 4 cycles, and all other instructions require

View solution

Q. If the stages are perfectly balanced, then the time per instruction on the pipelined processor, is equal to

View solution