Q. Total bits for a direct-mapped cache with data of 16 KB and blocks of 4-word, assuming a 32-bit address are

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Q. The address location in the main memory, is referred to as

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Q. Blocks to be placed at the upper level of the hierarchy scheme used, is from direct memory to

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Q. Cache level L2's write policy of the Intel Pentium P4, is characterized as

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Q. The subtraction of hit rate (1-hit rate) is known as

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Q. If an item is referenced once, then it again be referenced soon; given statement is stated by

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Q. Scheme having set, in the cache as a group of blocks, is known as

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Q. Flash memories have limited number of the block's write cycles, these cycles must be at least

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Q. The Cortex-A8 known as configurable core, which supports the computer instruction set architecture of

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Q. One-half of the address is first sent during the

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Q. Switching from one process to another. This swapping is called a

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Q. The very owns way for reducing capacity misses, is to increase

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Q. Cache not able of containing the entire blocks needed while execution of a program, is known as

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Q. When cache having size 32k, block-size 64 and set the associativity 4, will have cache index of

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Q. The cache with special address translation, is referred to as a

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Q. Fetching the words in simple order, but as the requested block word arrives, send it towards the processor, is known as

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Q. The index of instruction cache is

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Q. For paying an extra level of indirection for each memory access, the Virtual machine monitor maintains a

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Q. Storing the arrays as row by row order, is referred to as

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Q. Two processors running one is user process, other is operating system process, the latter is called

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