Q. A direct-mapped cache having a size of N and has the miss rate same as a two-way set-associative cache, of size

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Q. The block placement strategy, is if set associative/direct mapped, then this miss is called

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Q. When Cycle per instruction is 1.0, data accesses are 50% of the total instructions, and the miss penalty is 25clock-cycles and the miss rate having 2%, then the computer would the faster as,

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Q. The address spaces are typically broken into the fixed-size blocks, called

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Q. The rate of no of misses in a cache which is divided by whole number of memory-accesses, to the cache, is known as

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Q. The name given to the first or highest level of the memory-hierarchy, is known as

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Q. The physical-address that is coming to the cache is further divided into field/s:

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Q. If the cache is not able for containing all the blocks needed while execution, the miss is then known as

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Q. When the victim buffer is totally full, the cache must

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Q. 10% stores and 26% loads instruction for MIPS programs, to make writes

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Q. Larger blocks increases the conflict-misses and the capacity-misses, whenever the cache is

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Q. The page table level that says if page has been modified, is known as

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Q. Data structure, maintaining the addresses of physical-pages, typically takes the form of a

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Q. The matching tag sends the corresponding physical address through effectively a

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Q. For Reducing Miss Rate, using Large blocks', the given statement defines

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Q. Equivalent to the PTE valid bit, used to indicate the valid translation is refered to as

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Q. When the processor gets the requested data items from the cache, it is called a

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Q. To provide for protected sharing, half of the address space is shared by all processes and half is unique to each process, called

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Q. The processor's performance can be calculated as

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Q. At any instant it is possible to switch from one process to another, this exchange is called a

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