Q. Address translation cache is referred to as a

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Q. Cutting of physical-memory into the form of blocks and allocating them to different processes, the stated technique is known as

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Q. If the processor is not willing in the cycle for retiring the maximum number of instructions; it is said to be

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Q. The security loopholes, prevents by not allowing the user process to ask the operating system to access somethingindirectly are known as

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Q. When the processor is waiting for write instruction to complete during the write-through process, the processor is said to

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Q. If a set has n blocks, the cache placement is then called

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Q. For reducing the frequency on replacement of write-back blocks, the commonly used feature, is known as

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Q. The processor address's size, determines the size of

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Q. A direct-mapped cache having a size of N and has the miss rate same as a two-way set-associative cache, of size

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Q. The block placement strategy, is if set associative/direct mapped, then this miss is called

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Q. When Cycle per instruction is 1.0, data accesses are 50% of the total instructions, and the miss penalty is 25clock-cycles and the miss rate having 2%, then the computer would the faster as,

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Q. The address spaces are typically broken into the fixed-size blocks, called

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Q. The rate of no of misses in a cache which is divided by whole number of memory-accesses, to the cache, is known as

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Q. The name given to the first or highest level of the memory-hierarchy, is known as

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Q. The physical-address that is coming to the cache is further divided into field/s:

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Q. If the cache is not able for containing all the blocks needed while execution, the miss is then known as

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Q. When the victim buffer is totally full, the cache must

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Q. 10% stores and 26% loads instruction for MIPS programs, to make writes

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Q. Larger blocks increases the conflict-misses and the capacity-misses, whenever the cache is

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Q. The page table level that says if page has been modified, is known as

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