Q. The basic circuit ECL supports the

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Q. An adder-subtractor single unit can be designed using full adder and

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Q. Which of the following is not a universal building block ?

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Q. CARRY in half adder can be obtained using

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Q. A NAND gate has inputs A and B. It's output is connected to the both of the inputs of another NAND gate. An equivalent gate for these two NAND gates is

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Q. The operation which commutative but not associative is

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Q. In which of the following gates, the output is 1 if and only if at least one input is 1?

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Q. The inverter OR gate and AND gate are called decision-making elements because they can recognize some input _____ while disregarding others. A gate recognizes a word when its output is _____

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Q. The functional difference between SR flip-flop and JK flip-flop is that

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Q. With an RS latch a high S and low R sets the output to _____ ; a low S and a high R _____ the output to low.

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Q. Flip-flop outputs are always

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Q. A NOR gate has two or more input signals. All input must be _____ to get a high output.

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Q. An inverter is also called a _____ gate.

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Q. With a NAND latch a low R and a low S produce a _____ condition.

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Q. The simplified form of the Boolean expression (X + Y + XY)(X + Z) is

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Q. De Morgan's first theorem says that a NOR gate is equivalent to a bubbled _____ gate.

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Q. A combinational logic circuit which is used when it is desired to send data from two or more source through a single transmission line is known as

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Q. How many Flip-Flops are required for mod–16 counter?

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Q. The digital logic family which has minimum power dissipation is

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Q. Data can be changed from special code to temporal code by using

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