Q. The functional difference between SR flip-flop and JK flip-flop is that

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Q. With an RS latch a high S and low R sets the output to _____ ; a low S and a high R _____ the output to low.

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Q. Flip-flop outputs are always

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Q. A NOR gate has two or more input signals. All input must be _____ to get a high output.

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Q. An inverter is also called a _____ gate.

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Q. With a NAND latch a low R and a low S produce a _____ condition.

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Q. The simplified form of the Boolean expression (X + Y + XY)(X + Z) is

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Q. De Morgan's first theorem says that a NOR gate is equivalent to a bubbled _____ gate.

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Q. A combinational logic circuit which is used when it is desired to send data from two or more source through a single transmission line is known as

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Q. How many Flip-Flops are required for mod–16 counter?

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Q. The digital logic family which has minimum power dissipation is

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Q. Data can be changed from special code to temporal code by using

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Q. A ring counter consisting of five Flip-Flops will have

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Q. The speed of conversion is maximum in

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Q. The gates required to build a half adder are

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Q. If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is

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Q. The device which changes from serial data to parallel data is

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Q. A device which converts BCD to Seven Segment is called

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Q. The access time of ROM using bipolar transistors is about

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Q. The A/D converter whose conversion time is independent of the number of bits is

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