Q. A given memory chip has 14 address pins and 8 data pins. It has the following number of locations.

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Q. The instruction: MOV CL, [BX] [DI] + 8 represents the ............... addressing mode.

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Q. The power dissipation of a flip-flop is 3 mW. The power dissipation of a digital system with 4 flip-flops is given by

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Q. A binary ripple counter is required to count up to 16383. How many flip-flops are required ?

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Q. Which one of the following is not an addressing mode?

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Q. Computers can have instruction formats with

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Q. Which is not a typical program control instruction?

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Q. Interrupt which arises from illegal or erroneous use of an instruction or data is

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Q. Match the following:

a. TTL                 i. High component density
b. ECL               ii. Low power consumption
c. MOS               iii. Evolution of “diodetransistor- logic”
d. CMOS           iv. High speed digital circuits

Codes:
      a   b   c    d

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Q. The branch logic that provides making capabilities in the control unit is known as

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Q. Cached and interleaved memories are ways of speeding up memory access between CPU’s and slower RAM. Which memory models are best suited (i.e. improves the performance most) for which programs ?

(i) Cached memory is best suited for small loops.
(ii) Interleaved memory is best suited for small loops
(iii) Interleaved memory is best suited for large sequential code.
(iv) Cached memory is best suited for large sequential code.

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Q. Which of the following logic families is well suited for high-speed operations ?

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Q. A complete microcomputer system consists of

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Q. Where does a computer add and compare data ?

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Q. Pipelining strategy is called implement

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Q. The concept of pipelining is most effective in improving performance if the tasks being performed in different stages :

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Q. Identify the addressing modes of below instructions and match them :

(a) ADI (1) Immediate addressing
(b) STA (2) Direct addressing
(c) CMA (3) Implied addressing
(d) SUB (4) Register addressing

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Q. Identify the devices given below with their IC numbers :

(i) USART                                 (a) 8251
(ii) Micro controller                (b) 8051
(iii) Interrupt controller         (c) 8259
(iv) DMA controller                 (d) 8257

      (i)   (ii)    (iii) (iv)

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Q. On receiving an interrupt from an I/O device, the CPU

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Q. Consider a logical address space of 8 pages of 1024 words mapped with memory of 32 frames. How many bits are there in the physical address?

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