Q. Match the following:

Addressing Mode      Location of operand
a. Implied                      i. Registers which are in CPU
b. Immediate                 ii. Register specifies the address
of the operand
c. Register                     iii. Specified in the register
d. Register Indirect      iv. Specified implicitly in the
definition of instruction

Codes:
     a   b   c  d

View solution

Q. In 8085 microprocessor, the digit 5 indicates that the microprocessor needs

View solution

Q. In 8085, which of the following performs: load register pair immediate operation?

View solution

Q. The content of the accumulator after the execution of the following 8085 assembly language program, is

MVI A, 35H
MOV B, A
STC
CMC
RAR
XRA B

View solution

Q. A ripple counter is a (n):

View solution

Q. 8085 microprocessor has ............... bit ALU.

View solution

Q. The register that stores the bits required to mask the interrupts is ................

View solution

Q. Which of the following in 8085 microprocessor performs

HL = HL + HL ?

View solution

Q. In ............... addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction.

View solution

Q. Which of the following is a sequential circuit?

View solution

Q. 8085 microprocessor has ............. hardware interrupts.

View solution

Q. Which of the  following in 8085 microprocessor performs
HL = HL + DE ?

View solution

Q. The Register that stores all interrupt requests is:

View solution

Q. The ............... addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction.

View solution

Q. In ............. method, the word is written to the block in both the cache and main memory, in parallel.

View solution

Q. A Multicomputer with 256 CPUs is organized as 16x16 grid. What is the worst case delay (in hops) that a message might have to take?

View solution

Q. What will be the hexadecimal value in the register ax (32-bit) after executing the following instructions?

Mov al, 15
Mov ah, 15
Xor al, al
Mov cl, 3
Shr ax, cl

View solution

Q. What will be the output at PORT1 if the following program is executed?

MVI B, 82H
MOV A, B
MOV C, A
MVI D, 37H
OUT PORT1
HLT

View solution

Q. Which of the following 8085 microprocessor hardware interrupt has the lowest priority?

View solution

Q. A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes?

View solution