Q. A ripple counter is a (n):

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Q. 8085 microprocessor has ............... bit ALU.

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Q. The register that stores the bits required to mask the interrupts is ................

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Q. Which of the following in 8085 microprocessor performs

HL = HL + HL ?

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Q. In ............... addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction.

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Q. Which of the following is a sequential circuit?

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Q. 8085 microprocessor has ............. hardware interrupts.

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Q. Which of the  following in 8085 microprocessor performs
HL = HL + DE ?

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Q. The Register that stores all interrupt requests is:

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Q. The ............... addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction.

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Q. In ............. method, the word is written to the block in both the cache and main memory, in parallel.

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Q. A Multicomputer with 256 CPUs is organized as 16x16 grid. What is the worst case delay (in hops) that a message might have to take?

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Q. What will be the hexadecimal value in the register ax (32-bit) after executing the following instructions?

Mov al, 15
Mov ah, 15
Xor al, al
Mov cl, 3
Shr ax, cl

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Q. What will be the output at PORT1 if the following program is executed?

MVI B, 82H
MOV A, B
MOV C, A
MVI D, 37H
OUT PORT1
HLT

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Q. Which of the following 8085 microprocessor hardware interrupt has the lowest priority?

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Q. A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes?

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Q. A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?

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Q. A CPU handles interrupt by executing interrupt service subroutine.................

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Q. Which one of the following set of gates is best suited for ‘parity’ checking and ‘parity’ generation?

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Q. ................ refers to the discrepancy among a computed, observed or measured value and the true specified or theoretically correct values.

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