Q. ECL is the fastest of all logic families. High Speed in ECL is possible because transistors are used in difference amplifier configuration, in which they are never driven into ...............

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Q. A binary 3-bit down counter uses J-K flip-flops, FFi with inputs Ji, Ki and outputs Qi, i=0,1,2 respectively. The minimized expression for the input from following, is

I. J0=K0=0
II. J0=K0=1
III. J1=K1=Q0
IV. J1=K1=Q'0
V. J2=K2=Q1Q0
Vl. J2=K2=Q'1Q'0

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Q. Which of the following is an interrupt according to temporal relationship with system clock?

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Q. Match the following:

Addressing Mode      Location of operand
a. Implied                      i. Registers which are in CPU
b. Immediate                 ii. Register specifies the address
of the operand
c. Register                     iii. Specified in the register
d. Register Indirect      iv. Specified implicitly in the
definition of instruction

Codes:
     a   b   c  d

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Q. In 8085 microprocessor, the digit 5 indicates that the microprocessor needs

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Q. In 8085, which of the following performs: load register pair immediate operation?

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Q. The content of the accumulator after the execution of the following 8085 assembly language program, is

MVI A, 35H
MOV B, A
STC
CMC
RAR
XRA B

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Q. A ripple counter is a (n):

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Q. 8085 microprocessor has ............... bit ALU.

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Q. The register that stores the bits required to mask the interrupts is ................

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Q. Which of the following in 8085 microprocessor performs

HL = HL + HL ?

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Q. In ............... addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction.

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Q. Which of the following is a sequential circuit?

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Q. 8085 microprocessor has ............. hardware interrupts.

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Q. Which of the  following in 8085 microprocessor performs
HL = HL + DE ?

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Q. The Register that stores all interrupt requests is:

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Q. The ............... addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction.

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Q. In ............. method, the word is written to the block in both the cache and main memory, in parallel.

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Q. A Multicomputer with 256 CPUs is organized as 16x16 grid. What is the worst case delay (in hops) that a message might have to take?

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Q. What will be the hexadecimal value in the register ax (32-bit) after executing the following instructions?

Mov al, 15
Mov ah, 15
Xor al, al
Mov cl, 3
Shr ax, cl

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