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Question

For a pipelined CPU with a single ALU, consider the following situations

1. The j + 1-st instruction uses the result of the j-th instruction
as an operand
2. The execution of a conditional jump instruction
3. The j-th and j + 1-st instructions require the ALU at the same
time

Which of the above can cause a hazard ?

a.

1 and 2 only

b.

2 and 3 only

c.

3 only

d.

All of above

Answer: (d).All of above

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Q. For a pipelined CPU with a single ALU, consider the following situations 1. The j + 1-st instruction uses the result of the j-th instruction as an operand 2. The execution...

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