Q. The number of counters that are present in the programmable timer device 8254 is

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Q. The operation that can be performed on control word register is

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Q. The mode that is used to interrupt the processor by setting a suitable terminal count is

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Q. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low for

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Q. The generation of a square wave is possible in the mode

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Q. In control word register, if SC1=0 and SC0=1, then the counter selected is

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Q. In control word format, if RL1=1, RL0=1 then the operation performed is

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Q. If BCD=0, then the operation is

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Q. The counter starts counting only if

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Q. The control word register contents are used for

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Q. The number of hardware interrupts that the processor 8085 consists of is

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Q. The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is

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Q. The register that stores the bits required to mask the interrupt inputs is

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Q. The interrupt control logic

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Q. In a cascaded mode, the number of vectored interrupts provided by 8259A is

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Q. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a

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Q. Once the ICW1 is loaded, then the initialization procedure involves

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Q. When non-specific EOI command is issued to 8259A it will automatically

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Q. In the application where all the interrupting devices are of equal priority, the mode used is

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Q. The registers that store the keyboard and display modes and operations programmed by CPU are

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