Q. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low for

View solution

Q. The generation of a square wave is possible in the mode

View solution

Q. In control word register, if SC1=0 and SC0=1, then the counter selected is

View solution

Q. In control word format, if RL1=1, RL0=1 then the operation performed is

View solution

Q. If BCD=0, then the operation is

View solution

Q. The counter starts counting only if

View solution

Q. The control word register contents are used for

View solution

Q. The number of hardware interrupts that the processor 8085 consists of is

View solution

Q. The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is

View solution

Q. The register that stores the bits required to mask the interrupt inputs is

View solution

Q. The interrupt control logic

View solution

Q. In a cascaded mode, the number of vectored interrupts provided by 8259A is

View solution

Q. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a

View solution

Q. Once the ICW1 is loaded, then the initialization procedure involves

View solution

Q. When non-specific EOI command is issued to 8259A it will automatically

View solution

Q. In the application where all the interrupting devices are of equal priority, the mode used is

View solution

Q. The registers that store the keyboard and display modes and operations programmed by CPU are

View solution

Q. The sensor RAM acts as 8-byte first-in-first-out RAM in

View solution

Q. The registers that hold the address of the word currently being written by the CPU from the display RAM are

View solution

Q. When a key is pressed, a debounce logic comes into operation in

View solution