Q. The control word register contents are used for

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Q. The number of hardware interrupts that the processor 8085 consists of is

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Q. The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is

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Q. The register that stores the bits required to mask the interrupt inputs is

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Q. The interrupt control logic

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Q. In a cascaded mode, the number of vectored interrupts provided by 8259A is

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Q. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a

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Q. Once the ICW1 is loaded, then the initialization procedure involves

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Q. When non-specific EOI command is issued to 8259A it will automatically

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Q. In the application where all the interrupting devices are of equal priority, the mode used is

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Q. The registers that store the keyboard and display modes and operations programmed by CPU are

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Q. The sensor RAM acts as 8-byte first-in-first-out RAM in

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Q. The registers that hold the address of the word currently being written by the CPU from the display RAM are

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Q. When a key is pressed, a debounce logic comes into operation in

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Q. The mode that is programmed using “end interrupt/error mode set command” is

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Q. When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks whether the key is still depressed in

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Q. The data that is entered from the left side of the display unit is of

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Q. The FIFO status word is used to indicate the error in

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Q. The flag that increments automatically after each read or write operation to the display RAM is

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Q. If any change in sensor value is detected at the end of a sensor matrix scan, then the IRQ line

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