Q. The CPU must flush out the prefetched instructions immediately following the branch instruction in

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Q. The device that interface and control the internal data bus with the system bus is

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Q. The register bank of Execution Unit of 80286 is used as

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Q. Which of the following is not an interrupt generated by 80286?

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Q. For which of the following instruction does the return address point to instruction causing exception?

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Q. The instruction that comes into action, if the trap flag is set is

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Q. The interrupt that has the highest priority among the following is

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Q. The interrupt that has the lowest priority among the following is

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Q. The 80386 Microprocessor family is a _____ bit microprocessor.

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Q. In which year, 80386 microprocessor was introduced?

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Q. Which device is high-performance member of the 80386 family of MPUs?

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Q. The 80486 family was introduced in the year ______.

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Q. ________ maintains real modes protected-mode software compatibility with 80386 architecture.

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Q. 80486DX was followed by ________.

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Q. In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the
___________.

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Q. ________ bit in ICW1 indicates whether the 8259A is cascade mode or not ?

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Q. In 8279, a scanned sensor matrix mode, if a sensor changes its state, the __________ line goes ___________ to interrupt the CPU.

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Q. In 80186, the timer which connects to the system clock is

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Q. Which pins are general purpose I/O pins during mode-2 operation of the 82C55?

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Q. The fetching of the program from secondary memory to place it in physical memory, during the execution of CPU is called

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