Q. ________ bit in ICW1 indicates whether the 8259A is cascade mode or not ?

View solution

Q. In 8279, a scanned sensor matrix mode, if a sensor changes its state, the __________ line goes ___________ to interrupt the CPU.

View solution

Q. In 80186, the timer which connects to the system clock is

View solution

Q. Which pins are general purpose I/O pins during mode-2 operation of the 82C55?

View solution

Q. The fetching of the program from secondary memory to place it in physical memory, during the execution of CPU is called

View solution

Q. Which of the block is not considered as a block of an architecture of 80286?

View solution

Q. The device that interfaces and control the internal data bus with the system bus is

View solution

Q. For which of the following instruction does the return address point to instruction causing an exception?

View solution

Q. The 80286 is available in the package as

View solution

Q. The clock frequency applied at the CLK pin is internally divided by

View solution

Q. The 8 address lines, A23-A16 of 80286 are zero during

View solution

Q. The signals S1 (active low), S2 (active low) are

View solution

Q. If M/IO (active low) signal is ‘0’ then it indicates

View solution

Q. The LOCK (active low) is activated automatically by hardware using

View solution

Q. The pin that is used to insert wait states in a bus cycle is

View solution

Q. The minimum number of clock cycles required in an input pulse width of the RESET pin is

View solution

Q. To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins

View solution

Q. The signal that causes the 80286 to perform the processor extension interrupt while executing the WAIT and ESC instructions are

View solution

Q. The 80286 CPU acts just like that of 8086 when operated in

View solution

Q. In real addressing mode, the 80286 addresses a physical memory of

View solution