Q. ______ type circuits are generally used for interrupt service lines

i) open-collector
ii) open-drain
iii) XOR
iv) XNOR

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Q. The resistor which is attached to the service line is called _____.

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Q. An interrupt that can be temporarily ignored is

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Q. The 8085 microprocessor respond to the presence of an interrupt

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Q. CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged

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Q. Which interrupt is unmaskable…??

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Q. From amongst the following given scenarios determine the right one to justify interrupt mode of data transfer
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs

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Q. How can the processor ignore other interrupts when it is servicing one

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Q. When dealing with multiple device interrupts , which mechanism is easy to implement

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Q. The interrupt servicing mechanism in which the reqesting device identifies itself to the processor to be serviced is

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Q. Which table handle stores the addresses of the interrupt handling sub-routines

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Q. Interrupts initiated by an instruction is called as

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Q. The anded output of the bits of the interrupt register and the mask register are set as input of:

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Q. ____ register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.

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Q. ______ interrupt method uses register whose bits are set separately by interrupt signal for each device:

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Q. In daisy chaining device 0 will pass the signal only if it has..

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Q. _________ method is used to establish priority by serially connecting all devices that request an interrupt.

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Q. Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line…??
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices is possible.

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Q. The processor indicates to the devices that it is ready to recieve interrupts

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Q. The starting address sent by the device in vectored interrupt is called as

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