Question
a.
2Kbits
b.
3Kbits
c.
4Kbits
d.
8Kbits
Posted under Computer Architecture
Engage with the Community - Add Your Comment
Confused About the Answer? Ask for Details Here.
Know the Explanation? Add it Here.
Q. In the (0,2) branch predictor, having 4K entries, the bits are
Similar Questions
Discover Related MCQs
Q. A increasing scheme for the number of instructions, relative to the overhead and branch instructions is
View solution
Q. Allowing multiple instructions for issuing in a clock cycle, is the goal of
View solution
Q. For predicting the value which will be produced by an instruction, this stated technique is referred as
View solution
Q. Attempts for predicting the result of a computation used technique, is called
View solution
Q. In the scheme, named as Tomasulo
View solution
Q. Computing the miss penalties, for every system, the formula which can be used is
View solution
Q. The given instruction: L.D F0,0(R1), gets the state of execution in
View solution
Q. If f0 is the array element then adding the scalar in F2, can be calculated as
View solution
Q. When branches are being mis-predicted; hazard which is raised due to this issue, is known as
View solution
Q. Considering the following code: DIV.D F0,F2,F4; ADD.D F10,F0,F8; SUB.D F12,F8,F14, one statement that is true
View solution
Q. Branch predictors using the behavior of all other branches for making a prediction, are called
View solution
Q. Detection of loop stream r micro-fusion is performed by
View solution
Q. Branch-target buffer having a single variation for storing one or more target instructions instead, or in addition to the predicted
View solution
Q. Out-of-order execution of the program, tends to introduce the possibility of
View solution
Q. Three different types of dependences are
View solution
Q. The property of if a value of the executed instruction would be used by a coming instruction, is called
View solution
Q. The processor without the structural hazard is
View solution
Q. In the following instruction set DADD R1,R2,R3; DSUB R4,R1,R5; AND R6,R1,R7; OR R8,R1,R9; XOR R10,R1,R11, all the instructions after the DADD use the result of the
View solution
Q. If any instruction in A1, . . . , A4, D, M1, . . . , M7 has the same register destination as this instruction, then the possible solution is
View solution
Q. The simplest scheme to handle branches is to
View solution
Suggested Topics
Are you eager to expand your knowledge beyond Computer Architecture? We've curated a selection of related categories that you might find intriguing.
Click on the categories below to discover a wealth of MCQs and enrich your understanding of Computer Science. Happy exploring!
