adplus-dvertising
frame-decoration

Question

Multithreading allowing multiple-threads for sharing the functional units of a

a.

Multiple processor

b.

Single processor

c.

Dual core

d.

Corei5

Posted under Computer Architecture

Answer: (b).Single processor

Engage with the Community - Add Your Comment

Confused About the Answer? Ask for Details Here.

Know the Explanation? Add it Here.

Q. Multithreading allowing multiple-threads for sharing the functional units of a

Similar Questions

Discover Related MCQs

Q. The eliminating stage of WAR and WAW hazards, is often called

Q. The maximum performance measurement, attainable by the implementation is

Q. The goal of software techniques and hardware techniques, is to exploit

Q. A branch-prediction cache which is used to store the predicted address for the upcoming instruction after the branch, is called a

Q. Hardware-based speculation method for executing programs, is necessarily a

Q. When an instruction starts execution and when it ends execution; between these two times, the instruction is in

Q. The operation for performing on source operands, S1 and S2 is given by the well-known field,

Q. Simple technique which predicts if two stores or a load and a store referred to the exact memory address is called

Q. The actual dataflow values among instructions, which produce results and those that consume those results, is known as

Q. For every instruction present in the buffer, prediction accuracy is

Q. Between the instruction ADD.D and the instruction SUB.D, there is

Q. By-passing and Forwarding techniques, reduces the

Q. In the PARSEC benchmarks, SMT energy gets reduced by

Q. The final stage of completion of an instruction, after which merely the result remains, is known

Q. The execution time for the unrolled loop, has been dropped to a total of

Q. The most common, often implemented technique of multithreading, is called

Q. An alternative towards the fine-grained multithreading, the devised technique was

Q. In the (0,2) branch predictor, having 4K entries, the bits are

Q. A increasing scheme for the number of instructions, relative to the overhead and branch instructions is

Q. Allowing multiple instructions for issuing in a clock cycle, is the goal of