Q. The PTX instruction having format: opcode.type d, a, b, c; where d is the

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Q. When every unit is fully pipelined, and a new operation can be started on each clock-cycle known as

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Q. When elements are tends to be operated on in the dense form, then the sparse vector gets stored in an expanded form by a

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Q. The vector instructions which can be potentially executed altogether, is known as

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Q. If exploiting and finding the parallelism, across branches require scheduling code, a substantially very difficult algorithm is

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Q. Having load before the store in a running program order, then interchanging this order, results in a

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Q. When instruction i and instruction j are tends to write the same register or the memory location, it is called

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Q. Branch-selected entries in a (2,2) predictor, which is having a total of 8K-bits in the prediction buffer are

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Q. The 10-bit history is used for allowing patterns of up to

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Q. Predictors taking this insight to the following level, by the use of multiple predictors; by combining Local and global Predictors, are called

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Q. The local predictor contains the

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Q. Hazards are eliminated through register renaming by renaming all

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Q. Waiting until there is no data hazards, then

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Q. If straight-line code is generated by un-rolling, then this stated technique, is known as

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Q. The clock-cycle timings of the processors are 250 ps, 200 ps, and 400 ps, respectively, then it will have the miss penalties as

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Q. Load and store instruction, waits until the

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Q. The number of bits in a predictor: (m,n) is

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Q. Combination of instructions, such as compare following a branch and combining them into a one-operation, is taken by

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Q. The primary challenge for every multiple-issue processors is trying to exploiting large amount of

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Q. A special hardware buffer is required for the instruction execution sequence, that holds the instruction results, this process is known as

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