Q. The clock-cycle timings of the processors are 250 ps, 200 ps, and 400 ps, respectively, then it will have the miss penalties as

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Q. Load and store instruction, waits until the

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Q. The number of bits in a predictor: (m,n) is

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Q. Combination of instructions, such as compare following a branch and combining them into a one-operation, is taken by

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Q. The primary challenge for every multiple-issue processors is trying to exploiting large amount of

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Q. A special hardware buffer is required for the instruction execution sequence, that holds the instruction results, this process is known as

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Q. Determining the whole branch penalty for buffer of branch-target, assuming that the Hit rate and the Prediction accuracy is 90%

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Q. Multithreading allowing multiple-threads for sharing the functional units of a

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Q. The eliminating stage of WAR and WAW hazards, is often called

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Q. The maximum performance measurement, attainable by the implementation is

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Q. The goal of software techniques and hardware techniques, is to exploit

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Q. A branch-prediction cache which is used to store the predicted address for the upcoming instruction after the branch, is called a

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Q. Hardware-based speculation method for executing programs, is necessarily a

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Q. When an instruction starts execution and when it ends execution; between these two times, the instruction is in

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Q. The operation for performing on source operands, S1 and S2 is given by the well-known field,

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Q. Simple technique which predicts if two stores or a load and a store referred to the exact memory address is called

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Q. The actual dataflow values among instructions, which produce results and those that consume those results, is known as

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Q. For every instruction present in the buffer, prediction accuracy is

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Q. Between the instruction ADD.D and the instruction SUB.D, there is

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Q. By-passing and Forwarding techniques, reduces the

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