Q. A small page size will result in less wasted storage when a contiguous region of virtualmemory is not equal in size to a multiple of the page size, this unused memory is known as

View solution

Q. To help the operating system estimate LRU, many processors provide a

View solution

Q. The policy for memory hierarchies: L1 data are never found in an L2 cache, refers to

View solution

Q. The 64-bit virtual address of the AMD64 architecture is mapped onto

View solution

Q. A better measurement of performance of memory-hierarchy is the

View solution

Q. When the computer processor does not get a data item it requires in the cache, then the problem is known as

View solution

Q. To restrict entry into others

View solution

Q. Significant percentage of the spent time in moving data in two levels in the memory hierarchy, then the memory-hierarchy is said to

View solution

Q. The cache term is now applied when a buffering is employed for reusing commonly occurring items, for example

View solution

Q. If each block having one place to be appear in the cache, this cache is said to be

View solution

Q. In a direct-mapped cache of eight words (1)10 (00001two) and (29)10 (11101two) map to locations

View solution

Q. The levels between the CPU and main memory were given a name of

View solution

Q. Allowing the processor for continuing execution of instructions, that access data-cache while having cache miss, is known as

View solution

Q. Having 32-bit virtual-address, 4 KB pages and 4 bytes/page of table entry, the total no of page-table size would be

View solution

Q. A queue holding data while the data are waiting to be written in memory, is known as

View solution

Q. Cache having 64 blocks and a block-size of 16 bytes, will have block-no for address 1200 map to

View solution

Q. The spatial locality, is also known as

View solution

Q. In terms of the no of read accesses/program, the miss penalty in clock-cycles for a reading, and the reading miss-rate, is defined as

View solution

Q. Having a cache block of 4words, having one-word-wide bank of DRAMs and the miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be

View solution

Q. The range of designs between direct-mapped and fully-associative cache, is called

View solution