Q. In terms of the no of read accesses/program, the miss penalty in clock-cycles for a reading, and the reading miss-rate, is defined as

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Q. Having a cache block of 4words, having one-word-wide bank of DRAMs and the miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be

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Q. The range of designs between direct-mapped and fully-associative cache, is called

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Q. The main memory of a computer can act as a

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Q. If the entries no is a power of 2 in the cache, then modulo will be computed by using the

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Q. Forget to accounting the byte addressing or the cache block-size, in processing a cache is a

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Q. The principle of locality that was used; implementing memory of the computer as

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Q. The program of copying address of PTE into temp $k1 would be executed with the instruction

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Q. A field in the memory hierarchy table that indicates the associated block, is called a

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Q. A virtual-memory block is known as page, and a virtual-memory miss is called a

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Q. Latency clock rate of the AMD operation is,

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Q. The decimal address having reference 22 will have a Binary address of reference

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Q. Cache misses created by the 1st access to a block, that was not in the cache, is known as

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Q. A situation in which the same object is being accessed by two addresses, is referred to as

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Q. Hit-rate of the processor is the memory fraction, found in

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Q. Kernel mode in which the operating system's programs run is also known as

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Q. Total bits for a direct-mapped cache with data of 16 KB and blocks of 4-word, assuming a 32-bit address are

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Q. The address location in the main memory, is referred to as

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Q. Blocks to be placed at the upper level of the hierarchy scheme used, is from direct memory to

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Q. Cache level L2's write policy of the Intel Pentium P4, is characterized as

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