Q. The unit that performs scheduling of instructions by determining the data dependencies is

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Q. The pool of instructions that are fetched is stored in an addressable memory called

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Q. The microoperations that are converted by decoder are directly transferred to

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Q. The logical source(s) and logical destination(s) that the micro operation has respectively are

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Q. The decoder unit in fetch-decode unit converts the instructions into

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Q. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched instructions and decode them is

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Q. The unit that accepts the sequence of instructions from the instruction cache as input is

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Q. Which of the following is not an independent engine of Pentium-Pro?

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Q. The unit that is used to implement the multiple branch prediction in Pentium-Pro is

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Q. A dual independent bus has

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Q. The execution in which the consecutive instruction execution in a sequential flow is hampered is

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Q. The type of execution which means that the CPU should speculate which of the next instructions can be executed earlier is

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Q. Because of Pentium’s superscalar architecture, the number of instructions that are executed per clock cycle is

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Q. During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by

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Q. The instructions that pass through the fetch, decode and execution stages sequentially is known as

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Q. If the result of PCMPEQ, which is a comparison of two packed data types, is a success, then the mask generated is

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Q. The instruction in which both multiplication and addition are performed is

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Q. When the instruction, PMULHW, is performed, then the higher order 16-bits of the 32 bit products are stored in

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Q. When the instruction, PMULLW, is performed, then the lower order 16-bits of the 32 bit products are stored in

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Q. The instruction that is not operated on quad word is

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