Q. During the instruction cycle of 80386, any debug fault can be ignored if

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Q. The RF is not automatically reset after the execution of

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Q. The segment descriptor register is used to store

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Q. The 32-bit control register, that is used to hold global machine status, independent of the executed task is

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Q. The descriptor table that the 80386 supports is

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Q. The registers that are together, known as system address registers are

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Q. Which of the following is a system segment register?

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Q. The test register(s) that is provided by 80386 for page caching is

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Q. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are

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Q. The registers that are used to store four program controllable break point addresses are

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Q. The register DR6 hold

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Q. The flag bits that indicate the privilege level of current IO operations are

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Q. The registers that are not available for programmers are

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Q. Which of the following is not a scale factor of addressing modes of 80386?

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Q. Contents of an index register are multiplied by a scale factor that may be added further to get the operand offset in

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Q. Contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset in

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Q. In the based scaled indexed mode with displacement mode, the contents of an index register are multiplied by a scale factor and are added to

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Q. The following statement of ALP is an example of

MOV EBX, [EDX*4] [ECX].

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Q. The following statement is an example of

MOV EBX, LIST [ESI*2].
MUL ECX, LIST [EBP*4].

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Q. Bit field can be defined as a group of

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