Q. A more efficient way to organise a Page Table is by means of an associative memory having

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Q. If there are four ROM ICs of 8K and two RAM ICs of 4K words, than the address range of Ist RAM is (Assume initial addresses correspond to ROMs)

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Q. The idea of cache memory is based

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Q. If memory access takes 20 ns with cache and 110 ns with out it, then the ratio ( cache uses a 10 ns memory) is

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Q. In a memory-mapped I/O system, which of the following will not be there?

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Q. Virtual memory consists of

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Q. If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be

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Q. Memory unit accessed by content is called

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Q. The performance of cache memory is frequently measured in terms of a quantity called

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Q. The cache memory of 1K words uses direct mapping with a block size of 4 words. How many blocks can the cache accommodate?

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Q. A page fault

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Q. If a block can be placed at every location in the cache, this cache is said to be

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Q. For recording, was the block written, the Opteron keeps

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Q. The information when is written in the cache, both to the block in the cache and the block present in the lower-level memory, refers to

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Q. Average access time of memory for having memory-hierarchy performance is given as

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Q. As segment or a page is normally used for block, page-fault and the address-fault is used for

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Q. The block frame address are divided into the

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Q. The increase in the width of the cache address tag, can be done with the

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Q. The victim buffer's performance and the operation is almost similar to

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Q. Assume that the hit-time is single clock cycle, independent of size of block, and then 16-byte block in a 4 KB cache will be having access-time of

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