Q. Which of the following architecture is/are not suitable for realizing SIMD ?

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Q. CPU checks for an interrupt signal during

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Q. In a vectored interrupt

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Q. An instruction pipeline can be implemented by means of

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Q. A microprogram sequencer

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Q. Status bit is also called

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Q. If the value V(x) of the target operand is contained in the address field itself, the addressing mode is

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Q. The instructions which copy information from one location to another either in the processor’s internal register set or in the external main memory are called

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Q. Content of the program counter is added to the address part of the instruction in order to obtain the effective address is called

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Q. Which of the following interrupt is non maskable

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Q. In which addressing mode the operand is given explicitly in the instruction?

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Q. To load and store instructions of vector architectures, the unit used is

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Q. The most essential source of overhead, when gets ignored by the chime model is vector

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Q. The highest bandwidth of memory for moving the ridge point in the Corei7 from 2.6 to

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Q. The median vectorization getting improved from about 70% to about

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Q. Loops when gets vectored then they do not have dependences among iterations of a loop, which are called

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Q. Around 82% issues of the clock-cycle, have them between 29 to 32 out of the

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Q. The length of a vector operation in a real program is often

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Q. The processor of the system, which can read/write GPU Memory, is known as

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Q. The L1 data caches has a size between

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